Low-dispersion component in an electronic chip

ABSTRACT

A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

This application claims the priority benefit of French patentapplication number 16/56020, filed on Jun. 28, 2016, the content ofwhich is hereby incorporated by reference in its entirety to the maximumextent allowable by law.

BACKGROUND Technical Field

The present disclosure relates to the manufacturing of electroniccomponents such as integrated circuits and, more particularly, thepresent disclosure aims at forming within a semiconductor wafercomponents having a low dispersion with respect to one another.

Description of the Related Art

Integrated electronic circuits are generally manufactured fromsemiconductor wafers having a large number of identical electronic chipsformed therein, said chips being subsequently separated from oneanother, generally by sawing.

The manufacturing of electronic chips comprises a large number ofmasking steps, specific operations being carried out according to thepatterns of each mask, for example, dopant implantations, layeretchings, and electric connections in connection layers.

Conventionally, it can be observed that the electronic chips of a wafercontain elementary components such as capacitors, transistors, andmemory cells, which exhibit certain dispersions of characteristicsresulting from the manufacturing. In particular, a given component willnot always have the same value from one semiconductor wafer to another,nor from one chip to another of a same semiconductor wafer.

In certain cases, such dispersions are highly critical, for example,when tuning capacitors are desired to be manufactured.

To overcome such dispersions, many solutions have been used in priorart, such as:

imposing extremely strict constraints to the manufacturing method: thisis expensive and the obtained dispersion limit is generally only in theorder of ±7% within a wafer;

sorting the obtained chips and rejecting bad chips: this may cause anefficiency loss greater than 10% if all chips for which there is adispersion greater than ±5% are rejected; and/or

performing laser adjustments at the end of the manufacturing: this is ofcourse an expensive and lengthy technique.

Thus, methods enabling to decrease the manufacturing dispersion ofelectronic circuit chips to increase the manufacturing efficiency andavoid additional steps (sorting, laser adjustment . . . ).

BRIEF SUMMARY

Thus, an embodiment provides a method of manufacturing electronic chipscontaining low-dispersion components, comprising the steps of:

mapping the average dispersion of said components according to theirposition in test semiconductor wafers;

associating, with each component of each chip, auxiliary correctionelements;

activating by masking the connection of the correction elements to eachcomponent according to the initial mapping.

According to an embodiment, the components are capacitors and thecorrection elements are capacitors sharing an electrode with the maincapacitor.

According to an embodiment, the capacitors are formed between two dopedpolysilicon layers and are provided with a dielectric formed of asuccession of silicon oxide, nitride, and oxide layers.

According to an embodiment, the method provides step-and-repeat maskingsteps, one of the reticles being intended to ensure or not theconnections of the auxiliary components, and wherein said reticle isshifted by a variable step in addition to the normal step-and-repeatstep.

An embodiment provides a semiconductor wafer containing electronicchips, each chip comprising at least one component of a first type, thiscomponent being associated with auxiliary correction componentsconnected or not according to the position of the chip in the wafer.

According to an embodiment, the components of the first type arecapacitors and the auxiliary components are auxiliary capacitors sharingan electrode with the main capacitor and having surface areas muchsmaller than that of the main component, the auxiliary capacitors beingconnected or not according to the position of the chip in the wafer.

According to an embodiment, the capacitors are of ONO type.

An embodiment provides an integrated circuit chip obtained by sawing ofa wafer such as hereabove.

The foregoing and other features and advantages will be discussed indetail in the following non-limiting description of dedicatedembodiments in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 shows the value of tuning capacitors arranged in various chips ofa wafer according to the distance of these chips to the center of thewafer;

FIG. 2 illustrates a strategy of capacitance adjustment on a wafer;

FIG. 3 shows a first embodiment of a dispersion-compensated capacitorstructure;

FIG. 4 shows the shape of patterns obtained by a step-and-repeat methodon a silicon wafer; and

FIG. 5 shows a second embodiment of a dispersion-compensated capacitorstructure.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numeralsin the various drawings and, further, the various drawings are not toscale. For clarity, only those steps and elements which are useful tothe understanding of the described embodiments have been shown and aredetailed.

In the present description, to ease the understanding, only the specificcase where tuning capacitors having as a dielectric a siliconoxide-nitride-oxide three-layer and having their opposite electrodesmade of heavily-doped polysilicon will first be considered. Suchcapacitors will here be called ONO capacitors and may for example beused as tuning capacitors of a RF circuit. However, it should be notedthat this is not the only application of the methods described herein.

The inventors have studied the dispersion of capacitances of ONOcapacitors conventionally manufactured in a semiconductor wafer.

FIG. 1 shows, in ordinates, values of capacitance C and, in abscissas,distance r to the center of the semiconductor wafer of each chip havingat least one ONO capacitor manufactured therein. It can be observed thatif, for example, the capacitance value is 70 pF at the center of thechip, it decreases to a value of approximately 63 pF at the chipperiphery. This example is given in the case of a wafer having a 200-mmdiameter (8 inches).

FIG. 2 shows successive concentric areas of a semiconductor wafer. Itshould be noted that, if it is desired for all ONO capacitors to havethe same 70-pF value at the center and at the periphery of the wafer, itis desirable, in the context of the example of FIG. 1, to keep thecapacitors as such at the center (Add 0), to add 1 pF (Add 1p) to thecapacitors located in the first ring, 2 pF (Add 2p) to the capacitorslocated in the next ring, 3 pF (Add 3p) to the capacitors located in thenext ring, 4 pF (Add 4p) to the capacitors located in the next ring, 5pF (Add 5p) to the capacitors located in the next ring, 6 pF (Add 6p) tothe capacitors located in the next ring, and 7 pF (Add 7p) to thecapacitors located in the last ring. Of course, such a division intoseven areas is given as an example only. A finer division (more areas)or a rougher division (less areas) may be selected.

As illustrated in FIG. 3, it is here provided to form each capacitor ashaving a single lower plate 10 and a plurality of upper plates C, C1,C2, C3. The lower and upper plates are for example made of dopedpolysilicon. Upper plate C has a surface area capable of providing, atthe center of a wafer, a main capacitor C of desired capacitance, 70 pFin the example given herein. In this example, upper plates C1, C2, C3correspond to auxiliary capacitors respectively having capacitances of4, 2, and 1 pF.

A first connection metallization 11 extends between a contact, such as aconductive via in contact with lower plate 10, and a first node A of thecapacitor. Connection metallizations 12, 13, 14, and 15 extend betweenconductive contacts on each of upper plates C, C1, C2, and C3 and pads22, 23, 24, 25. Pads 22, 23, 24, 25 extend above a metallization 20 fromwhich they are separated by an insulating layer, not shown.Metallization 20 is connected by a metallization connection 31 to asecond node B of the capacitor.

According to whether contact pads 23, 24, 25 are placed or not incontact with metallization 20, one may add to capacitor C capacitors inparallel C1 and/or C2 and/or C3 to be able to add values in the rangefrom 1 to 7 pF to the basic capacitor. This is done by masking. For allpads 23-25, a conductive via 33-35 is formed or not between each of thepads and metallization 20. All pads 22 are connected to metallization 20by a conductive via 32. It should be noted that the fact that the upperplates of auxiliary capacitors C1, C2, C3 are always present, be theyconnected or not, enables to streamline the manufacturing, all the wafercapacitors being made in the same way. Only the mask corresponding to astep of definition of vias 33-35 is modified according to the wafer areawhere the capacitor is located.

The above example is particularly simple and corresponds to the casewhere a single mask is used to manufacture all the chips of a wafer. Itshould be noted that various embodiments may be selected to place inparallel at least one of capacitors C1, C2, C3 with capacitor C.Connections 13-15 for example may or not be interrupted.

Actually, step-and-repeat methods are generally used to manufactureintegrated circuits: masks or reticles are manufactured and the reticlesare displaced from one area to the other of the wafer.

Each of the squares illustrated in FIG. 4 corresponds to the dimensionof the reticle which will be repeated. Each square generally comprises aplurality of chips, for example, 1,000. The squares corresponding toeach of the ring-shaped areas of FIG. 2 will contain capacitors of samevalues, and this value will be shifted from the center to the peripheryof the wafer according to areas (Add 0), (Add 1p), (Add 2p), (Add 3p),(Add 4p), (Add 5p), (Add 6p), and (Add 7p) described in relation withFIG. 2.

A problem is that, when a step-and-repeat method is used, all reticlepatterns are identical given that the reticle cannot be modified fromone repetition to the next one.

FIG. 5 illustrates an embodiment of the auxiliary capacitor correctionconnections. In the example of FIG. 5, four capacitors C, C1, C2, C3 andrear conductive plate 10 connected, as previously, by a metallization 11to a node A (first electrode of the capacitor) have been shown.Metallizations 12, 13, 14, and 15 connected to each of the upperconductive layers of capacitors C, C1, C2, C3 are connected, as shown asan example, to a sequence of pads arranged parallel to one another.Connection 12 is connected to a single elongated pad 51. Connection 13is connected to one of two elongated pads 61 and 62 extending along halfthe length of pad 51. Connection 14 is connected to two alternated padsamong four pads 71, 72, 73, 74 having half the length of pads 61 and 62and extending parallel thereto. The last connection 15 to capacitor C3is connected to four alternated pads among eight pads 81-88. The padsrest on an insulating layer (not shown) that is on elongatedmetallization strips 91, 92, 93, 94 interconnected by a metallization 95corresponding to terminal B of the capacitor.

An example of locations to which the pads are connected or not byconductive vias through the insulating layer to the metallization formedunder them has been shown by a line of vertically-aligned black squares.Pad 51 is always connected by a contact (a black square) to theunderlying metallization, that is, terminal B always takes into accountcapacitor C. In the shown example, pad 61, connected to metallization13, is also connected to underlying metallization 92, that is, capacitorC1 is arranged in parallel with capacitor C. Pad 72 is arranged at alocation such that it is not connected to metallization 14. This meansthat capacitor C2 is not arranged in parallel on capacitors C and C1.However, pad 83 is connected to the underlying metallization, the padbeing connected to metallization 15. Thus, capacitor C3 is arranged inparallel with capacitor C. Accordingly, in this example, only capacitorsC, C1, and C3 are connected in parallel, that is, in the context of thegiven numerical example, 4+1 pF are added to capacitance C (the valuesof capacitors C1 and C3).

It should be understood that, according to the horizontal shift of therow of vias, all values between 0 and 7 pF may be added to thecapacitance of capacitor C. A specific mask determines the positions ofthe rows of vias and it is possible, in a step-and-repeat process, toslightly shift the step-and-repeat distance between two successiverepetitions. This enables to shift the rows of vias. The shifting stepmay be 100 nm only in current advanced technologies.

An example where the shifting of the rows of vias is horizontal, itshould however be understood that other configurations using verticalshifts or combinations of horizontal and vertical shifts may beselected. Thus, it is possible to obtain ONO capacitors which all have asame value, at the center as well as at the periphery of a semiconductorwafer. This is obtained without adding any additional manufacturingstep, but only, in the example given hereabove, by slightly shifting theposition of a mask during a step-and-repeat process.

As indicated at the beginning of the present disclosure, a specificexample where ONO capacitors, for example used as tuning capacitors is aradio frequency circuit, are formed, has been given. The inventors haveobserved that the type of constant dispersion between the center and theperiphery of a semiconductor wafer described in relation with FIG. 1appears for other components. Such a dispersion may exist for MOStransistors, for memory cells, for capacitors other than ONO capacitors,for example, MOS capacitors, or MIM (metal-insulator-metal) capacitors.In the case of MIM capacitors, the distribution of the capacitor valuesis substantially the same on a wafer (varying from the center to theperiphery) as in the case of ONO capacitors. The inventors have observedthat in other components, the distribution may be different.

Thus, the present disclosure generally provides a method ofmanufacturing an electronic chip containing low-dispersion componentscomprising the steps of mapping the average dispersion of saidcomponents according to their position in test semiconductor wafers;associating correction elements with each component of each chip; andconnecting by masking correction elements to each component according tosaid initial mapping.

It should also be understood that the present disclosure applies toother masking processes than those which have been described herein.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present disclosure. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting.

The various embodiments described above can be combined to providefurther embodiments. These and other changes can be made to theembodiments in light of the above-detailed description. In general, inthe following claims, the terms used should not be construed to limitthe claims to the specific embodiments disclosed in the specificationand the claims, but should be construed to include all possibleembodiments along with the full scope of equivalents to which suchclaims are entitled. Accordingly, the claims are not limited by thedisclosure.

What is claimed is:
 1. An electronic chip made by a method thatcomprises: manufacturing auxiliary correction elements on a plurality ofchips, respectively, the plurality of chips containg matchingcomponents, respectively; for each chip, selectively activating bymasking a connection of the auxiliary correction element of the chip tothe matching component of the chip in accordance with a mapping of astatistical dispersion of corresponding test components of testsemiconductor wafers according to positions of the corresponding testcomponents on the test semiconductor wafers, the test componentscorresponding to the matching components.
 2. The electronic chip ofclaim 1, wherein the matching components are main capacitors and theauxiliary correction elements are capacitors each sharing an electrodewith the main capacitor belonging to the same chip.
 3. The electronicchip of claim 2, wherein each of the main capacitors includes two dopedpolysilicon layers and a dielectric formed of a succession of siliconoxide, nitride, and oxide layers.
 4. The electronic chip of claim 1,wherein the method includes step-and-repeat masking steps usingreticles, one of the reticules being configured to selectively connectthe auxiliary correction elements with the matching components,respectively, and wherein said step-and-repeat mask steps includeshifting the one of the reticles by a variable step.
 5. The electronicchip of claim 1, wherein, for each chip: the matching component is amain capacitor having first and second electrodes; the auxiliarycorrection element includes first and second correction capacitors eachhaving first and second electrodes; the first electrodes of the firstand second correction capacitors are contiguous with the first electrodeof the main capacitor; and the second electrodes of the main capacitorand first and second correction capacitors are spaced apart from eachother.
 6. The electronic chip of claim 5, wherein, for each chip, themethod includes: forming a metallization adjacent to the main capacitorand the first and second correction capacitors; forming first and secondterminals of the main capacitor, the first terminal being electricallycoupled to the first electrode of the main capacitor and the secondterminal being electrically coupled to the metallization; forming aninsulating layer on the metallization; forming a conductive main pad andconductive first and second pads on the insulating layer; and forming amain conductive via extending through the insulating layer andelectrically connecting the main pad to the metallization, wherein theselectively activating includes forming an auxiliary conductive viaextending through the insulating layer and electrically connecting themetallization to one of the first and second pads, thereby connectingone of the first and second correction capacitors in parallel with themain capacitor between the first and second terminals.
 7. The electronicchip of claim 5, wherein, for each chip, the method includes: formingfirst, second, and third metallizations adjacent to the main capacitorand the first and second correction capacitors; forming first and secondterminals of the main capacitor, the first terminal being electricallycoupled to the first electrode of the main capacitor and the secondterminal being electrically coupled to the first, second, and thirdmetallizations; forming a conductive main pad electrically coupled tothe first metallization layer; forming first and second conductive padsinsulated from the second metallization, the first conductive pad beingelectrically coupled to the second electrode of the first correctioncapacitor and the second conductive pad being electrically insulatedfrom the second electrode of the first correction capacitor; and formingthird, fourth, fifth, and sixth conductive pads insulated from the thirdmetallization, the third and fifth conductive pads being electricallycoupled to the second electrode of the second correction capacitor andthe fourth and sixth conductive pads being electrically insulated fromthe second electrode of the second correction capacitor, wherein theselectively activating includes electrically connecting one of the firstand second conductive pads to the second metallization and electricallyconnecting one of the third, fourth, fifth, and sixth conductive pads tothe third metallization, thereby connecting at least one of the firstand second correction capacitors in parallel with the main capacitorbetween the first and second terminals.
 8. The electronic chip of claim7, wherein: the first, second, and third metallization extend lengthwiseparallel to each other in a first direction; the third and fourthconductive pads are aligned with portions of the first conductive padand portions of the main conductive pad in a second directionperpendicular to the first direction; the fifth and sixth conductivepads are aligned with portions of the second conductive pad and portionsof the main conductive pad in the second direction; and the selectivelyactivating includes electrically connecting the main conductive pad tothe first metallization by a first connector, electrically connectingone of the first and second pads to the second metallization by a secondconnector, and electrically connecting one of the third, fourth, fifth,and sixth conductive pads to the third metallization by a thirdconnector that is aligned with the first and second connectors in thesecond direction.
 9. A semiconductor wafer comprising electronic chips,each chip including a component of a first type and one or moreauxiliary correction components associated with the component, the oneor more auxiliary correction components being connected or not to thecomponent according to a position of the chip in the wafer.
 10. Thewafer of claim 9, wherein, for each chip, the component of the firsttype is a main capacitor and the one or more auxiliary components areauxiliary capacitors sharing an electrode with the main capacitor andhaving surface areas smaller than a surface area of the main component.11. The wafer of claim 10, wherein the main and auxiliary capacitors areONO capacitors.
 12. The wafer of claim 9, wherein, for each chip: thematching component is a main capacitor having first and secondelectrodes; the correction element includes first and second correctioncapacitors each having first and second electrodes; the first electrodesof the first and second correction capacitors are contiguous with thefirst electrode of the main capacitor; and the second electrodes of themain capacitor and first and second correction capacitors are spacedapart from each other.
 13. The wafer of claim 12, further comprising foreach chip: a metallization adjacent to the main capacitor and the firstand second correction capacitors; first and second terminals of the maincapacitor, the first terminal being electrically coupled to the firstelectrode of the main capacitor and the second terminal beingelectrically coupled to the metallization; an insulating layer on themetallization; a conductive main pad and conductive first and secondpads on the insulating layer; a main conductive via extending throughthe insulating layer and electrically connecting the main pad to themetallization; and an auxiliary conductive via extending through theinsulating layer and electrically connecting the metallization to one ofthe first and second pads, thereby connecting one of the first andsecond correction capacitors in parallel with the main capacitor betweenthe first and second terminals.
 14. The wafer of claim 12, furthercomprising for each chip: first, second, and third metallizationsadjacent to the main capacitor and the first and second correctioncapacitors; first and second terminals of the main capacitor, the firstterminal being electrically coupled to the first electrode of the maincapacitor and the second terminal being electrically coupled to thefirst, second, and third metallizations; a conductive main padelectrically coupled to the first metallization layer; first and secondconductive pads insulated from the second metallization, the firstconductive pad being electrically coupled to the second electrode of thefirst correction capacitor and the second conductive pad beingelectrically insulated from the second electrode of the first correctioncapacitor; and third, fourth, fifth, and sixth conductive pads insulatedfrom the third metallization, the third and fifth conductive pads beingelectrically coupled to the second electrode of the second correctioncapacitor and the fourth and sixth conductive pads being electricallyinsulated from the second electrode of the second correction capacitor,wherein one of the first and second conductive pads is electricallycoupled to the second metallization depending on the position of thechip within the wafer and one of the third, fourth, fifth, and sixthconductive pads is electrically coupled to the third metallizationdepending on the position of the chip within the wafer, therebyconnecting at least one of the first and second correction capacitors inparallel with the main capacitor between the first and second terminals.15. The wafer of claim 14, wherein: the first, second, and thirdmetallization extend lengthwise parallel to each other in a firstdirection; the third and fourth conductive pads are aligned withportions of the first conductive pad and portions of the main conductivepad in a second direction perpendicular to the first direction; thefifth and sixth conductive pads are aligned with portions of the secondconductive pad and portions of the main conductive pad in the seconddirection; the main conductive pad is electrically coupled to the firstmetallization by a first connector; the main conductive pad iselectrically coupled to the first metallization by a first connector;one of the first and second pads is electrically coupled to the secondmetallization by a second connector; and one of the third, fourth,fifth, and sixth conductive pads is electrically coupled to the thirdmetallization by a third connector that is aligned with the first andsecond connectors in the second direction.
 16. An integrated circuitchip, comprising: a main capacitor having first and second electrodes; afirst correction capacitor having first and second electrodes, the firstelectrode of the first correction capacitor being contiguous with thefirst electrode of the main capacitor, and the second electrodes of themain capacitor and first correction capacitor being spaced apart fromeach other; a metallization adjacent to the main capacitor and the firstcorrection capacitor; first and second terminals, the first terminalbeing electrically coupled to the first electrode of the main capacitorand the second terminal being electrically coupled to the metallization;an insulating layer on the metallization; a conductive main pad andconductive first and second pads on the insulating layer; a mainconductive via extending through the insulating layer and electricallyconnecting the main pad to the metallization; and a first auxiliaryconductive via extending through the insulating layer and electricallyconnecting the metallization to one of the first and second conductivepads.
 17. The integrated circuit chip of claim 16, wherein: themetallization includes first and second metallizations lines; the mainpad is directly over the first metallization line and the mainconductive via electrically connections the main pad to the firstmetallization line; the first and second conductive pads are directlyover the second metallization line and the first auxiliary conductivevia connects one of the first and second conductive pads to the secondmetallization line.
 18. The integrated circuit chip of claim 17, whereinthe metallization includes a third metallization line, the integratedcircuit chip further comprising: a second correction capacitor havingfirst and second electrodes, the first electrode of the secondcorrection capacitor being contiguous with the first electrodes of themain capacitor and the first correction capacitor, and the secondelectrodes of the main capacitor and first and second correctioncapacitors being spaced apart from each other; third, fourth, fifth, andsixth conductive pads directly over the third metallization line, thethird and fifth conductive pads being electrically coupled to the secondelectrode of the second correction capacitor and the fourth and sixthconductive pads being electrically insulated from the second electrodeof the second correction capacitor, wherein one of the third, fourth,fifth, and sixth conductive pads is electrically coupled to the thirdmetallization line.
 19. The integrated circuit chip of claim 18,wherein: the first, second, and third metallization lines extendlengthwise parallel to each other in a first direction; the third andfourth conductive pads are aligned with portions of the first conductivepad and portions of the main conductive pad in a second directionperpendicular to the first direction; the fifth and sixth conductivepads are aligned with portions of the second conductive pad and portionsof the main conductive pad in the second direction; one of the third,fourth, fifth, and sixth conductive pads is electrically coupled to thethird metallization by a second auxiliary conductive via that is alignedwith the main and first auxiliary conductive vias in the seconddirection.